1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacture thereof.
2. Description of the Related Art
In recent years, NAND type flash memories have been widely used as electrically erasable nonvolatile semiconductor memories. The NAND type flash memory contains a large number of NAND cell units, each of which is configured such that multiple memory cells are connected in series between select transistors. Each of the memory cells has its gate connected to a control gate line (word line) and each of the select transistors has its gate connected to a select gate line.
In the NAND type flash memory, the select gate lines are usually set greater in width than the control gate lines. That is, the control gate lines are arranged at the same pitch, while the select gate lines are arranged at a pitch different from the pitch of the control gate lines. Thus, the select gate lines disturbs the periodicity of line arrangement. As a result, when the dimensions of semiconductor devices are scaled down, the exposure margin in lithographic processes lowers, making it difficult to form patterns for control gate lines and select gate lines with great accuracy. That is, it becomes difficult to form patterns for the gate structures of memory cells and select transistors with great accuracy.
Japanese Unexamined Patent Publication No. 2003-51557 discloses a structure in which one select gate line large in width is replaced with two select gate lines each of which is equal in width to the control gate line. This structure allows the select gate lines to be arranged at the same pitch as the control gate lines. However, since two select gate lines (two select transistors) are used in place of one select gate line (select transistor), there arises a problem of time displacement in operation between the two select transistors.
In the NAND type flash memory, a bit line contact is usually formed in an interlayer insulating film formed between adjacent select transistors. However, when the dimensions of semiconductor devices are scaled down, it becomes difficult to reliably form the interlayer insulating film between the gate structures of adjacent select transistors. That is, voids are easily formed in the interlayer insulating film, making it difficult to perfectly fill the space between the gate structures of adjacent select transistors with the interlayer insulating film.
Thus, conventional problems are that difficulties are involved in forming patterns for the gate structures of memory cells and select transistors with great accuracy and in forming an interlayer insulating film between the gate structures of adjacent select transistors with certainty.